1. Field of the Invention
This invention relates to a semiconductor wafer, semiconductor chip, and method of inspection of a semiconductor chip, and in particular relates to a semiconductor wafer, semiconductor chip, and method of inspection of a semiconductor chip which are suitable for sorting defective chips arising from chipping during wafer cutting.
2. Description of the Related Art
Semiconductor wafers generally comprise scribe areas provided at equal intervals vertically and horizontally, and chip areas surrounded by scribe areas; as shown in FIG. 12A, pads 102a are arranged in the edge portions of the chip area 102 to connected the circuitry formed within to the outside. After forming the desired circuitry in the chip area 102, a dicing system or similar is used to cut the semiconductor wafer along the scribe center lines 103a, to form semiconductor chips 101.
Here, the dicing system physically cuts the semiconductor wafer by moving a thin disc-shaped cutting edge (blade), rotating at high speed, along scribe center lines 103a; hence the cut face is not flat, but a minute roughness (chipping) occurs, as in FIG. 12B. Because of this, the cutting groove (kerf) is set such that the chipping remains within the scribe area 103; but if there is deviation from the dicing conditions or if the blade is degraded, the chipping may increase to reach the chip areas 2, as a result of which damage (chip 108) may occur in semiconductor chips 101, cracks 109 may occur, visible defects may result, wiring lines may be broken, and there may be damage to pads 102a and circuits, among other problems.
Hence in the related art, a CCD camera provided in the dicing system is used to capture images of the cutting faces, and image processing is performed to observe the kerf state as appropriate, and the quantity and temperature of the cutting water which cools the blade are adjusted, damaged and worn blades are replaced, and similar. But using this method, the range of images obtained in one measurement is small, and the measurement data is discontinuous; and data obtained by image capture includes much useless data, so that there is the problem that time is required for data processing and analysis. In order to resolve these problems, Japanese Unexamined Patent Application Publication No. 2002-333309 (hereafter, Related Art Example 1) discloses a chipping measurement method comprising a process of irradiating an area wider than the standard kerf width, in which, at least, chipping does not occur, with a slit-shaped optical beam; a process of receiving the reflected light from the work face; and a process of measuring the kerf chipping state according to the amount of light received.
There are also methods which do not use optical techniques, but measure a physical quantity (resistance) which changes in correlation with the kerf width. For example, Japanese Unexamined Patent Application Publication No. 3-222446 (hereafter, Related Art Example 2), as shown in FIG. 13, discloses a semiconductor wafer comprising, within a scribe area 103 extending in one direction among the scribe areas 103, a pair of metal wiring layers 110 formed in parallel along the scribe area 103 and electrode pads 110a formed at both ends of the metal wiring layers 110. Japanese Unexamined Patent Application Publication No. 3-222447 (hereafter, Related Art Example 3) discloses a structure in which, in place of the above metal wiring layers, a pair of resistance layers, including one type of conductive impurity, are provided. By using such metal wiring layers 110 and resistance layers, when the blade is degraded and the kerf width increases, the resistance of the metal wiring layers 110 or of the resistance layers including the impurity becomes high, or the conduction path is broken, so that by measuring the resistance blade degradation can be inferred, and defects caused by chipping can be prevented.
By using the methods described in the above Related Art Examples 2 and 3, compared with methods in which the kerf shape is observed, blade degradation can be predicted by simple means. In the above methods, however, metal wiring layers 110 and resistance layers including an impurity are formed within the scribe areas 103, so that as a result of dicing, even if the metal wiring layers 110 and resistance layers are cut, all that is learned is that the blade has degraded and the kerf width has increased, but it is not possible to determine whether chips 108 and cracks 109 occurring due to dicing remain within the scribe areas 103, or extend to the chip areas 102.
In order to predict blade degradation, it is not necessary to form the above metal wiring layers 110 or resistance layers in all the scribe areas 103. Hence even in the above Related Art Examples 2 and 3, metal wiring layers 110 and resistance layers are provided only in a scribe area 103 in one direction at one edge of the semiconductor wafer. Hence even if chips 108 or cracks 109 occurred in scribe areas in the other direction, and the chips 108 or cracks 109 reached the chip areas 102 adjacent to the scribe area 103, defective chips could not be sorted.
Further, in the above Related Art Examples 2 and 3, the metal wiring layers 110 and resistance layers are formed from one end to the other end of the semiconductor wafer. Specifically, the layers are formed spanning a plurality of semiconductor chips 101, so that even if the resistance of the metal wiring layers 110 and resistance layers increased due to chips 108 and cracks 109, it is not possible to determine at what position the metal wiring layers 110 and resistance layers are cut or broken, and the result of resistance measurement cannot be used in pass/fail determinations of individual semiconductor chips.
Moreover, as a problem arising from dicing, in addition to the chips 108 and cracks 109 occurring during dicing, even if a chip 108 or crack 109 is within the range of tolerable sizes immediately after dicing, stresses, shocks, and thermal cycles occurring during mounting of the semiconductor chip 101, as well as stresses, shocks, thermal cycles and similar occurring after product assembly, may cause chips 108 to increase in size and cracks 109 to progress, to reach the interior of the semiconductor chip 1 with the passage of time. However, in the above Related Art Examples 2 and 3 it is assumed that the resistance is measured immediately after dicing, and the metal wiring layers 110 and resistance layers as well as the electrode pads 110a formed on the ends thereof are also formed within the scribe areas 103, so that the resistance cannot be measured at a desired time after chip mounting, and there is the problem that effective information cannot be provided with respect to chips 108 and cracks 109 which progress with the passage of time as described above.